Intel is to ditch the front side bus in a new version of its Xeon processor in a change which is expected to extend to many of its other processors, according to US reports. It is also reported to be delaying the new Montecino version of its Itanium processor until the middle of next year and reduced its top speed from 2GHz to 1.6GHz.

Both moves are something of a climbdown for Intel. The front side bus is the major artery of Intel architecture, connecting the processor indirectly to the Ram via the northbridge chip, which contains the memory controller. It is seen as the main reason rival AMD has been able gain the edge with its processors which have an onboard memory controller and talk directly to Ram.

So by scrapping the FSB, Intel is ignominiously following AMD's lead - something it has already had to do with the transition to 64bit. It still massively outsells AMD, but the latter has been eating into its market share.

The high-end Itanium, cruelly nicknamed Itanic, has never had the market success Intel hoped for though the company repeatedly points out that it is not addressing a high-volume market. It does not use the classic x86 PC instruction set and faces compeition in many of its markets from AMD's Opteron and, iornically, Intel's own Xeons.

Information Week reports that the Montecino flavour is being delayed from early to mid-2006 to 'ensure that it hits quality expectations' and will not include Foxton technology to minimise power consupmton and heat by controlling clock speed.

Also it will come with a 400MHz or 533MHz FSB rather than a predicted 667MHz and will clock a maximum 1.6GHz rather than 2GHz.