AMD lift the lid on Quad Core - The Test Bed

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AMD lift the lid on Quad Core

We got a glimpse of the future, when AMD held a briefing concerning their Quad Core Opteron CPU’s, due for launch in 2007. Built on a 65mn process, the native quad cores (coded K8L) are going to be direct pin replacements for Socket F Opteron’s with the same power and thermal envelopes as Socket F dual core CPU's.
They will use a Silicon-on-Insulator process which allows fast transistors with low power leakage to be used which helps reduce wasted power and heat, and to further improve energy savings each core can be run at different speeds or turned off completely by using the new Enhanced Power Now feature. An enhanced Crossbar Switch will enable different parts of the cores to be accessed at the same time.

The integrated memory controller (DDR2) and the new Direct Connect Architecture 2.0 will allow for faster HyperTransport speeds and is already able to support 8 core processors.

At present each core will come with 64KB/64KB L1 cache, 512KB of L2 cache and the new shared L3 cache (2Mb+) can be expanded.
Although the server based Socket F based CPU’s will be the first to arrive, AM2 desktop and mobile versions are in the pipeline.

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